Power Electronics

Layout-induced gate-loop inductance remains the dominant cause of false turn-on in fast GaN half-bridges. We measure sixteen board revisions across a 3 nH to 21 nH loop range and show that overshoot scales almost linearly with loop inductance until the sink impedance of the driver dominates. A practical layout rule is derived, together with the measurement fixture needed to verify it without disturbing the loop under test.

A sealed enclosure can sit 25 K above ambient long before anything looks wrong, and electrolytic life halves for every 10 K. This note gives the internal-rise measurement method, a worked derating example for a 40 W supply, and the ripple-current budget that follows from it.

Returns from three years of desert deployment were disassembled and traced to root cause. Sixty-one per cent of failures resolved to a single connector series whose retention degraded under daily thermal cycling, not to the semiconductors that the original FMEA had ranked highest. The revised FMEA weighting is included.