Gate-Loop Inductance and Ringing in 650 V GaN Half-Bridges

Abstract

Layout-induced gate-loop inductance remains the dominant cause of false turn-on in fast GaN half-bridges. We measure sixteen board revisions across a 3 nH to 21 nH loop range and show that overshoot scales almost linearly with loop inductance until the sink impedance of the driver dominates. A practical layout rule is derived, together with the measurement fixture needed to verify it without disturbing the loop under test.